diff --git a/arch/arm/mach-rockchip/sdram_common.c b/arch/arm/mach-rockchip/sdram_common.c
index 76dbdc8..19f7c17 100644
--- a/arch/arm/mach-rockchip/sdram_common.c
+++ b/arch/arm/mach-rockchip/sdram_common.c
@@ -14,7 +14,7 @@
 DECLARE_GLOBAL_DATA_PTR;
 size_t rockchip_sdram_size(phys_addr_t reg)
 {
-	u32 rank, col, bk, cs0_row, cs1_row, bw, row_3_4;
+        u32 rank, col, bk, cs0_row, cs1_row, bw, row_3_4, dbw, bg;
 	size_t chipsize_mb = 0;
 	size_t size_mb = 0;
 	u32 ch;
@@ -37,16 +37,20 @@ size_t rockchip_sdram_size(phys_addr_t reg)
 			SYS_REG_BW_MASK));
 		row_3_4 = sys_reg >> SYS_REG_ROW_3_4_SHIFT(ch) &
 			SYS_REG_ROW_3_4_MASK;
+     		dbw = sys_reg >> SYS_REG_DBW_SHIFT(ch) & SYS_REG_DBW_MASK;
+                /* only used by DDR4 */
+                bg = (dbw == 1) ? 1 : 2;
 
-		chipsize_mb = (1 << (cs0_row + col + bk + bw - 20));
+                chipsize_mb = (1 << (cs0_row + col + bg + bk + bw - 20));
 
 		if (rank > 1)
 			chipsize_mb += chipsize_mb >> (cs0_row - cs1_row);
 		if (row_3_4)
 			chipsize_mb = chipsize_mb * 3 / 4;
 		size_mb += chipsize_mb;
-		debug("rank %d col %d bk %d cs0_row %d bw %d row_3_4 %d\n",
-		      rank, col, bk, cs0_row, bw, row_3_4);
+                debug("rank %d col %d bk %d cs0_row %d bw %d row_3_4 %d dbw %d\n",
+                     rank, col, bk, cs0_row, bw, row_3_4, dbw);
+
 	}
 
 	return (size_t)size_mb << 20;
